The invention relates to a semiconductor circuit arrangement having a substrate, which carries in the order specified:                a doped semiconductor layer of a first conductivity type or conduction type,        an electrically insulating layer,        and an electrically conductive or an electrically insulating charge-storing layer, which is suitable for the storage of charges.        
Moreover, the semiconductor circuit arrangement contains at least one trench which penetrates through the charge-storing layer and also extends into the doped semiconductor layer.
The substrate is for example a wafer made of a semiconductor material, e.g. made of silicon. The layer suitable for the storage of charges is also referred to as floating gate particularly in the case of circuit arrangements having memory cells.
It is an object of the invention to specify an integrated circuit arrangement which is simple to fabricate and simple to drive and, in particular, has very good electrical properties. In particular, the intention is to specify a circuit arrangement having a multiplicity of memory cells. Moreover, the invention relates to a method which can be used, in particular, to fabricate the semiconductor circuit arrangement.
The invention is based on the consideration that there are in principle two possibilities for fabricating the trench. Thus, it is possible to fabricate the trench, apart from auxiliary layers which are completely removed again after the formation of the trench, before the application of layers which remain in the circuit arrangement, so that the trench does not penetrate through these layers. On the other hand, it is possible to introduce the trench only after layers which remain in the circuit arrangement have been applied to the substrate, so that the trench penetrates through these layers.
The invention is furthermore based on the consideration that the production of the trench after the application of layers which remain in the circuit arrangement simultaneously permits the patterning of these layers and the orientation of the trench with respect to the patterned regions, i.e. a so-called self-alignment. However, it is possible for the trench to be assigned further functions in the integrated circuit arrangement. In the circuit arrangement according to the invention, the trench also serves, moreover, for subdividing the doped semiconductor layer. This requires the trench to be deeper than the thickness of the doped semiconductor layer. Thus, in the circuit arrangement according to the invention, the trench also has, besides the insulating function for insulating adjacent components, two further functions, namely:                the patterning of the charge-storing layer, and        the patterning and insulation of the doped semiconductor layer.        
In one refinement, the circuit arrangement contains a plurality of trenches arranged next to one another, for example trenches lying parallel to one another.
Arranged between the trenches are in each case a multiplicity of memory cells, in particular EEPROM memory cells or flash EEPROM memory cells (Electrically Erasable Programmable Read Only Memory). In a next refinement, the charge-storing layer is subdivided into charge-storing regions transversely with respect to the direction in which the trenches lie.